1. Field of the Invention
The invention relates to the process of designing and fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for improving lithography performance by correcting for three dimensional (3D) mask effects.
2. Related Art
The relentless miniaturization of integrated circuits has been a key driving force behind technological innovations. This miniaturization has been made possible by rapid improvements in various fabrication technologies.
Unfortunately, as integration densities of semiconductor chips continue to increase at an exponential rate, it is becoming progressively harder to deal with various 3D mask effects that arise during lithography.
In particular, phase shift masks (PSMs) suffer from a 3D mask effect called “phase imbalance”. Note that a PSM contains phase shifters, which enable the fabrication process to achieve line widths that are smaller than the wavelength of the light used to expose the photoresist layer through the mask. Phase imbalance can be caused by the imperfect 3D structure of a shifter and the diffraction of light by the edge of the shifter. This can result in unwanted distortions in the printed pattern that, in turn, can result in low fabrication yields and large performance variations.
Hence, what is needed is a method and an apparatus for correcting for 3D mask effects.